? 2000 fairchild semiconductor corporation ds010581 www.fairchildsemi.com august 1989 revised august 2000 100304 low power quint and/nand gate 100304 low power quint and/nand gate general description the 100304 is monolithic quint and/nand gate. the function output is the wire-nor of all five and gate out- puts. all inputs have 50 k ? pull-down resistors. features low power operation 2000v esd protection pin/function compatible with 100104 voltage compensated operating range = ? 4.2v to ? 5.7v available to industrial grade temperature range (plcc package only) ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. logic symbol pin descriptions logic equation connection diagrams 24-pin dip 28-pin plcc order number package number package description 100304PC n24e 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.400 wide 100304qc v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square 100304qi v28a 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square industrial temperature range ( ? 40 c to + 85 c) pin names description d na ? d ne data inputs f function output o a ? o e data outputs o a ? o e complementary data outputs f = (d 1a d 2a ) + (d 1b d 2b ) + (d 1c d 2c ) + (d 1d d 2d ) + (d 1e d 2e ).
www.fairchildsemi.com 2 100304 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ? recommended operating conditions ? table will define the conditions for actual device operation. note 2: esd testing conforms to mil-std-883, method 3015. commercial version dc electrical characteristics (note 3) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = 0 c to + 85 c note 3: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. dip ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd plcc ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd storage temperature (t stg ) ? 65 c to + 150 c maximum junction temperature (t j ) + 150 c v ee pin potential to ground pin ? 7.0v to + 0.5v input voltage (dc) v ee to + 0.5v output current (dc output high) ? 50 ma esd (note 2) 2000v case temperature (t c ) commercial 0 c to + 85 c industrial ? 40 c to + 85 c supply voltage (v ee ) ? 5.7v to ? 4.2v symbol parameter min typ max units conditions v oh output high voltage ? 1025 ? 955 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1705 ? 1620 mv or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1035 mv v in = v ih(min) loading with v olc output low voltage ? 1610 mv or v il (max) 50 ? to ? 2.0v v ih input high voltage ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 av in = v il (min) i ih input high current d 2a ? d 2e 250 av in = v ih (max) d 1a ? d 1e 350 i ee power supply current ? 69 ? 43 ? 30 ma inputs open symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min max min max min max t plh propagation delay 0.40 1.75 0.40 1.65 0.40 1.75 ns t phl d na ? d ne to o, o figures 1, 2 t plh propagation delay 1.00 2.60 1.00 2.60 1.15 3.20 ns t phl data to f t tlh transition time 0.35 1.20 0.35 1.20 0.35 1.20 ns t thl 20% to 80%, 80% to 20% symbol parameter t c = 0 ct c = + 25 ct c = + 85 c units conditions min max min max min max t plh propagation delay 0.40 1.55 0.40 1.45 0.40 1.55 ns t phl d na ? d ne to o, o figures 1, 2 t plh propagation delay 1.00 2.40 1.00 2.40 1.15 3.00 ns t phl data to f t tlh transition time 0.35 1.10 0.35 1.15 0.35 1.10 ns t thl 20% to 80%, 80% to 20%
3 www.fairchildsemi.com 100304 industrial version plcc dc electrical characteristics (note 4) v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd, t c = ? 40 c to + 85 c note 4: the specified limits represent the ? worst case ? value for the parameter. since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. conditions for testing sho wn in the tables are cho- sen to guarantee operation under ? worst case ? conditions. plcc ac electrical characteristics v ee = ? 4.2v to ? 5.7v, v cc = v cca = gnd symbol parameter t c = ? 40 ct c = 0 c to + 85 c units conditions min max min max v oh output high voltage ? 1085 ? 870 ? 1025 ? 870 mv v in = v ih (max) loading with v ol output low voltage ? 1830 ? 1575 ? 1830 ? 1620 or v il (min) 50 ? to ? 2.0v v ohc output high voltage ? 1095 ? 1035 mv v in = v ih(min) loading with v olc output low voltage ? 1565 ? 1610 or v il (max) 50 ? to ? 2.0v v ih input high voltage ? 1170 ? 870 ? 1165 ? 870 mv guaranteed high signal for all inputs v il input low voltage ? 1830 ? 1480 ? 1830 ? 1475 mv guaranteed low signal for all inputs i il input low current 0.50 0.50 av in = v il (min) i ih input high current d 2a ? d 2e 250 250 av in = v ih (max) d 1a ? d 1e 350 350 i ee power supply current ? 69 ? 30 ? 69 ? 30 ma inputs open symbol parameter t c = 40 ct c = + 25 ct c = + 85 c units conditions min max min max min max t plh propagation delay 0.35 1.55 0.40 1.45 0.40 1.55 ns figures 1, 2 t phl d na ? d ne to o, o t plh propagation delay 1.00 2.40 1.00 2.40 1.15 3.00 ns t phl data to f t tlh transition time 0.35 1.10 0.35 1.15 0.35 1.10 ns t thl 20% to 80%, 80% to 20%
www.fairchildsemi.com 4 100304 test circuitry notes: v cc , v cca = + 2v, v ee = ? 2.5v l1 and l2 = equal length 50 ? impedance lines r t = 50 ? terminator internal to scope decoupling 0.1 f from gnd to v cc and v ee all unused outputs are loaded with 50 ? to gnd c l = fixture and stray capacitance 3 pf figure 1. ac test circuit switching waveforms figure 2. propagation delay and transition times
5 www.fairchildsemi.com 100304 physical dimensions inches (millimeters) unless otherwise noted 24-lead plastic dual-in-line package (pdip), jedec ms-010, 0.400 wide package number n24e
www.fairchildsemi.com 6 100304 low power quint and/nand gate physical dimensions inches (millimeters) unless otherwise noted (continued) 28-lead plastic lead chip carrier (plcc), jedec mo-047, 0.450 square package number v28a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
